Due to the increased portion of Static Random Access Memory (SRAM) arrays in the total chip area of modern chips, device dimensions in SRAM must be continuously scaled. However, SRAM stability degrades rapidly with scaled devices. Various methods have been employed to maintain stability but generally at the cost of performance, density and design assist overhead. For example, one approach is to use asymmetric SRAM cells to improve stability with one-sided sensing. In this approach, the wordline is split into a wordline left (WL) and a wordline right (WR). The SRAM can be read on one side only with either the WR or the WL. In this way, during read operation only the word line of the sensing side is activated.
Although stability can be enhanced with asymmetric designs, the SRAM cell is not useful for differential sensing. That is, the SRAM cell is not useful for SRAM designs with standard differential sensing from a bitline left (BL) and a bitline right (BR). Asymmetric designs also impose undesirable constraints on the SRAM applications. For example, the bit line on one side cannot be used as a 2nd read port. This effectively slows down the read/write operations. Also, the SRAM cell cannot serves as standard cell type where the asymmetric stability is not needed. Power down scheme in low power applications gets more complicated or compromised.